Search results for "video pipe"

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eISP, une architecture de calcul programmable pour l'amélioration d'images sur téléphone portable.

2009

4 pages; Today's smart phones, with their embedded high-resolution video sensors, require computing capacities that are too high to easily meet stringent silicon area and power consumption requirements (some one and a half square millimeters and half a watt) especially when programmable components are used. To develop such capacities, integrators still rely on dedicated low resolution video processing components, whose drawback is low flexibility. With this in mind, our paper presents eISP {--} a new, fully programmable Embedded Image Signal Processor architecture, now validated in {TSMC~65nm} technology to achieve a capacity of {16.8~GOPs} at {233~MHz}, for {1.5~mm$^2$} of silicon area and…

[ INFO.INFO-TS ] Computer Science [cs]/Signal and Image Processinglow power[INFO.INFO-TS] Computer Science [cs]/Signal and Image ProcessingCMOS[ SPI.SIGNAL ] Engineering Sciences [physics]/Signal and Image processingeISPSIMDvideo pipeimage processing[INFO.INFO-MC]Computer Science [cs]/Mobile ComputingMulti-SIMD[INFO.INFO-MC] Computer Science [cs]/Mobile Computing[INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing[ INFO.INFO-MC ] Computer Science [cs]/Mobile Computing[SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing[SPI.SIGNAL] Engineering Sciences [physics]/Signal and Image processing
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eISP: a Programmable Processing Architecture for Smart Phone Image Enhancement

2009

4 pages; Today's smart phones, with their embedded high-resolution video sensors, require computing capacities that are too high to easily meet stringent silicon area and power consumption requirements (some one and a half square millimeters and half a watt) especially when programmable components are used. To develop such capacities, integrators still rely on dedicated low resolution video processing components, whose drawback is low flexibility. With this in mind, our paper presents eISP {--} a new, fully programmable Embedded Image Signal Processor architecture, now validated in {TSMC 65nm} technology to achieve a capacity of {16.8 GOPs} at {233 MHz}, for {1.5 mm$^2$} of silicon area and…

[ INFO.INFO-TS ] Computer Science [cs]/Signal and Image Processinglow power[INFO.INFO-TS] Computer Science [cs]/Signal and Image ProcessingCMOSdemosaïcking[ SPI.SIGNAL ] Engineering Sciences [physics]/Signal and Image processingeISPmm²SIMDimage processingvideo pipesmall siliconMulti-SIMDcomputing tilemilliwatt[INFO.INFO-TS]Computer Science [cs]/Signal and Image ProcessingsensordemosaicingTSMC 65nm[SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing[SPI.SIGNAL] Engineering Sciences [physics]/Signal and Image processing
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